In a television broadcasting, a television character multiplexing broadcasting is proposed in which the vertical blanking period of a main television program is utilized to broadcast various kinds of information such as news, weather forecast, notice and so on.
In a receiver for receiving such broadcast, the display apparatus thereof is constructed as shown in FIG. 1.
In FIG. 1, when a pattern data to be displayed is received, this display pattern data is processed by a CPU 1 and then written in a pattern memory 2. In this pattern memory 2, its addresses Axy are schematically shown in response to a display picture screen as shown in FIG. 1. In this case, a horizontal address (address in the horizontal direction) Ax corresponds to the horizontal scanning position of the display picture screen, while a line address (address in the vertical direction) Ay corresponds to the vertical scanning position, or the horizontal line (scanning line), wherein EQU Axy=a.multidot.Ay+Ax
is established in which a corresponds to the lateral width of the display picture screen and for example, EQU a=32
Each bit of the memory 2 corresponds to each dot of a display pattern and a bit having level "1" is displayed as a dot (bright point).
A control circuit 6 generates an address signal which designates the horizontal address Ax, namely, a horizontal address signal HAS which is incremented one by one for every one byte (8 bits) of the pattern data in synchronism with the horizontal scanning and also an address signal which designates the line address Ay, namely, a line address signal LAS which is incremented one by one at every one horizontal scanning. By these address signals HAS and LAS, the memory 2 is addressed and pattern data is read out one byte by one byte from the address corresponding to the scanning position of the display picture screen.
The pattern data thus read is loaded in parallel one byte by one byte to a shift register 3 and then serially derived one bit by one bit therefrom. The pattern data thus derived is supplied to a CRT display 5. Accordingly, displayed on the screen of the CRT display 5 is a pattern which corresponds to the bit image of the memory 2.
By the way, when such display is carried out, in order to make such displayed pattern easy to see, it is proposed to carry out smoothing (rounding) in, for example, published Japanese patent application No. 41016/1978.
FIG. 2 schematically shows an example of a pattern data of a character "A" written in the pattern memory 2. In this pattern data, the hatched bits represent level "1", while the bits without hatching represent level "0".
FIG. 3 shows the character "A" which is displayed on the screen of the CRT display 5, in which no smoothing is carried out. Reference numerals L.sub.1 to L.sub.14 designate lines (scanning lines) in which the lines shown by solid lines are formed during the odd field periods, while the lines shown by broken lines are formed during the even field periods. Reference letter Du designates a dot having a fundamental size. Since the pattern data (FIG. 2) of the memory 2 is used during both the odd and even field periods, the display pattern becomes as shown in the figure.
On the contrary, when the smoothing is carried out, the character "A" is displayed as shown in FIG. 4, in which a half dot Dh having a width 1/2 the original dot Du is added. Accordingly, as compared with the character "A" which is not subjected to the smoothing as shown in FIG. 3, this character becomes smooth and easy to see.
When this smoothing is carried out, the combination of the half dot Dh with the unit dot Du can exist only in two ways as shown in FIG. 5, and in all patterns, the half dot Dh is added to the unit dot in the combinations shown in FIG. 5. That is, when the two unit dots Du are arranged in the oblique direction, the two half dots Dh are added in the direction intersecting the above oblique direction.
Accordingly, when the smoothing processing is carried out, during the odd field period the pattern data on the line (the line address Ay of the memory 2 is n address) which is currently displayed and the pattern data on the preceding line (Ay=n-1) are required, while during the even field period, the pattern data on the line (Ay =n) which is currently displayed and the pattern data on the succeeding line (Ay=n+1) are necessary.
For this reason, when the smoothing is carried out, the access of the pattern data for the pattern memory 2 is generally carried out as shown in FIG. 6.
FIG. 6 shows a certain horizontal period, in which Tb represents the horizontal blanking period, Th the horizontal display period (horizontal scanning period) and Tp a period which corresponds to the lateral width of the pattern data of one byte (see FIG. 1). The horizontal address Ax (the signal HAS) is incremented one address by one address at every period Tp in response to the horizontal scanning position, while the line address Ay (the signal LAS) is designated as n' address in the former half period Tpf of the period Tp and n address in the latter half period Tpb thereof, in which n represents the line address Ay (=n) corresponding to the line which is currently displayed and n' is represented as: EQU n'=n-1 . . . odd field period EQU n'=n+1 . . . even field period
In consequence, from the memory 2 during the latter half period Tpb, derived is the pattern data (hereinafter simply called "display data DD") on the line (Ay=n) which is currently displayed and during the first half period Tpf, the pattern data (hereinafter called "comparing data DR") on the preceding or succeeding line (Ay=n-1 or Ay=n+1).
These data DD and DR are loaded to shift registers 3D and 3R as shown in FIG. 7 and then made simultaneous. Then, the data DD and DR thus made simultaneous to each other are subjected to the smoothing process by a processing circuit 4 from which a luminance signal having the half dot Dh as shown in FIG. 5 is produced and which then is delivered to the CRT display 5.
However, in such smoothing processing, the memory 2 is always addressed by the control circuit 6 for reading during the period Th so that the CPU 1 can access the memory 2 only during the period Tb, or the latency time of the CPU 1 becomes long, thus the apparent processing speed and processing ability of the CPU 1 being lowered, which is inconvenient.
If the period (Tpf +Tpb) is made shorter than the period Tp, the CPU 1 can access the memory 2 during the remaining period. To this end, this processing requires the memory 2 of extremely high speed which is difficult to be realized. If such high speed memory is realized, it becomes very expensive.
In order to obtain the comparing data DR, the line address Ay indicated by the line address signal LAS must be n' address which is displaced by one address from n address and its value n' becomes different in the displacing direction depending on the odd field period and even field period, it is necessary to provide a complex address converting circuit.
Therefore, it is an object of this invention to provide a display apparatus capable of reducing the latency time of the CPU in the smoothing processing and which is free from the increase of the cost.